1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, for example, a semiconductor integrated circuit device including a transistor used by applying a substrate bias.
2. Background Art
In recent years, variations in manufacturing processes among CMOS devices have increased as CMOS becomes finer, increasing variations in performance among IC chips.
When designing ICs, it is necessary to consider both of the worst condition of an operating rate and the worst condition of power consumption. An increase of variations in performance among IC chips makes it difficult to respond to the worst conditions, so that IC designs may become more difficult.
As a technique for suppressing variations in performance among IC chips, a substrate bias technique has been known. In such a substrate bias technique, a substrate potential (back gate) is set higher than a source potential and a substrate bias of a forward bias is generated, so that the threshold voltage of a transistor is controlled.
In this case, the forward bias is generated by, for example, connecting a voltage source to a substrate node. However, since a PN junction is present between a substrate and a source, a substrate voltage exceeding a forward voltage drop causes a large leakage current on the substrate. Further, the forward voltage drop changes with temperatures and a large leakage current occurs at high temperatures at a substrate voltage lower than 0.6 V which is a forward voltage drop at room temperature. For this reason, the substrate voltage has to be sufficiently smaller (e.g., 0.45 V) than 0.6 V in consideration of a temperature change.
Another known method is, for example, to pass current through a substrate by means of a current source circuit and use, as a substrate bias, a forward voltage generated on a PN junction (for example, see Japanese Patent Laid-Open No. 2004-289107). In this method, a predetermined amount of current is passed through the PN junction, so that even when a temperature changes, it is possible to apply the maximum allowable substrate bias at each temperature.
In this method, when the control signal of the current source circuit fluctuates because of the influence of crosstalk noise and the like, the amount of substrate current may considerably change.
Although it is necessary to estimate the amount of substrate current according to the size of a logic circuit (PN junction area), a ratio of a logic circuit area to an integrated circuit area (the utilization of a cell) may vary for each integrated circuit or the circuit design of an integrated circuit may be repeatedly changed in response to the retry and optimization of logic synthesis, so that it is difficult to identify the size of the logic circuit. Therefore, it is not easy to estimate the amount of substrate current according to the size of the logic circuit.